km616s4110c family cmos sram preliminary revision 0.01 august 1998 1 document title 256kx16 bit low power and low voltage cmos static ram revision history revision no 0.0 0.01 remark preliminary history initial draft errata correction draft date june 26, 1998 august 17, 1998 the attached datasheets are provided by samsung electronics. samsung electronics co., ltd. reserve the right to change the speci fications and products. samsung electronics will answer to your questions about device. if you have any questions, please contact the samsung branch offices.
km616s4110c family cmos sram preliminary revision 0.01 august 1998 2 256kx16 bit low power and low voltage cmos static ram general description the km616s4110c families are fabricated by samsung s advanced cmos process technology. the families support industrial operating temperature ranges and have chip scale package for user flexibility of system design. the families also support low data retention voltage for battery back-up operation with low data retention current. features process technology: tft organization: 256k x16 power supply voltage km616s4110c family: 2.3~2.7v low data retention voltage: 2.0v(min) three state output and ttl compatible dual cs and standby control by ub , lb package type: 48-csp name function name function cs 1 ,cs 2 chip select inputs vcc power oe output enable input vss ground we write enable input ub upper byte(i/o 9 ~ 16 ) a 0 ~a 17 address inputs lb lower byte(i/o 1 ~ 8 ) i/o 1 ~i/o 16 data inputs/outputs nc no connection product family 1. the parameter is measured with 30pf test load. product family operating temperature vcc range speed(ns) power dissipation pkg type standby (i sb1 , max) operating (i cc2 , max) km616s4110cli-l industrial(-40~85 c) 2.3~2.7v 100 1) /120 15 m a 25ma 48-csp samsung electronics co., ltd. reserves the right to change products and specifications without notice. functional block diagram clk gen. row selec i/o 1 ~i/o 8 data cont data cont data cont i/o 9 ~i/o 16 vcc vss precharge circuit. memory array 1024 rows 256 16 columns i/o circuit column select pin description 48-ball csp - top view (ball down) lb oe a0 a1 a2 cs2 i/o9 ub a3 a4 cs 1 i/o1 i/o10 i/o11 a5 a6 i/o2 i/o3 vss i/o12 a17 a7 i/o4 vcc vcc i/o13 n.c a16 i/o5 vss i/o15 i/o14 a14 a15 i/o6 i/o7 i/o16 n.c a12 a13 we i/o8 n.c a8 a9 a10 a11 n.c 1 2 3 4 5 6 a b c d e f g h we oe ub cs 1 lb control logic cs2 row addresses column addresses
km616s4110c family cmos sram preliminary revision 0.01 august 1998 3 product list industrial temp products(-40~85 c) part name function KM616S4110CLZI-10L km616s4110clzi-12l 48-csp, 100ns, 2.5v, ll 48-csp, 120ns, 2.5v, ll absolute maximum ratings 1) 1. stresses greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. functional oper ation should be restricted to recommended operating condition. exposure to absolute maximum rating conditions for extended periods may affect re liability. item symbol ratings unit voltage on any pin relative to vss v in ,v out -0.5 to v cc +0.5 v voltage on vcc supply relative to vss v cc -0.3 to 4.6 v power dissipation p d 1.0 w storage temperature t stg -65 to 150 c operating temperature t a -40 to 85 c functional description 1. x means don t care. (must be low or high state) cs 1 cs 2 oe we lb ub i/o 1~8 i/o 9~16 mode power h x 1) x 1) x 1) x 1) x 1) high-z high-z deselected standby x 1) l x 1) x 1) x 1) x 1) high-z high-z deselected standby x 1) x 1) x 1) x 1) h h high-z high-z deselected standby l h h h l x 1) high-z high-z output disabled active l h h h x 1) l high-z high-z output disabled active l h l h l h dout high-z lower byte read active l h l h h l high-z dout upper byte read active l h l h l l dout dout word read active l h x 1) l l h din high-z lower byte write active l h x 1) l h l high-z din upper byte write active l h x 1) l l l din din word write active
km616s4110c family cmos sram preliminary revision 0.01 august 1998 4 recommended dc operating conditions 1) note: 1. t a =-40 to 85 c, otherwise specified 2. overshoot: v cc +1.0v in case of pulse width 10ns 3. undershoot: -1.0v in case of pulse width 10ns 4. overshoot and undershoot are sampled, not 100% tested. item symbol product min typ max unit supply voltage vcc km616s4110c family 2.3 2.5 2.7 v ground vss all family 0 0 0 v input high voltage v ih km616s4110c family 2.0 - vcc+0.3 2) v input low voltage v il km616s4110c family -0.3 3) - 0.6 v capacitance 1) (f=1mhz, t a =25 c) 1. capacitance is sampled, not 100% tested item symbol test condition min max unit input capacitance c in v in =0v - 8 pf input/output capacitance c io v io =0v - 10 pf dc and operating characteristics item symbol test conditions min typ max unit input leakage current i li v in =vss to vcc -1 - 1 m a output leakage current i lo cs 1 =v ih, cs 2 =v il or oe =v ih or we =v il , v io =vss to vcc -1 - 1 m a operating power supply current i cc i io =0ma, cs 1 =v il, cs 2 =v ih , v in =v ih or v il - - 1 ma average operating current i cc1 cycle time=1 m s, 100%duty, i io =0ma, cs 1 0.2v, cs 2 3 vcc- 0.2v, v in 0.2v or v in 3 vcc-0.2v - - 4 ma i cc2 cycle time=min, i io =0ma, 100% duty, cs 1 =v il , cs 2 =v ih, vin=v il or v ih - - 25 ma output low voltage v ol i ol = 0.5ma 0.4 v output high voltage v oh i oh = -0.5ma 2.0 v standby current(ttl) i sb cs 1 =v ih , cs 2 =v il , other inputs=v ih or v il - - 0.3 ma standby current(cmos) i sb1 cs 1 3 vcc-0.2v, cs 2 3 vcc-0.2v( cs 1 controlled) or cs 2 0.2v(cs 2 controlled), other inputs=0~vcc - - 15 m a
km616s4110c family cmos sram preliminary revision 0.01 august 1998 5 c l 1 ) 1.including scope and jig capacitance ac operating conditions test conditions (test load and input/output reference) input pulse level: 0.4 to 2.2v input rising and falling time: 5ns input and output reference voltage:1.1v output load(see right): c l =100pf+1ttl c l =30pf+1ttl data retention characteristics 1. cs 1 3 vcc-0.2v,cs 2 3 vcc-0.2v( cs 1 controlled) or cs 2 3 vcc-0.2v(cs 2 controlled) item symbol test condition min typ max unit vcc for data retention v dr cs 1 3 vcc-0.2v 1) 2.0 - 2.7 v data retention current i dr vcc=2.5v, cs 1 3 vcc-0.2v 1) - 0.5 15 m a data retention set-up time t sdr see data retention waveform 0 - - ms recovery time t rdr 5 - - ac characteristics (vcc=2.3~2.7v, t a =-40 to 85 c) parameter list symbol speed bins units 100ns 120ns min max min max read read cycle time t rc 100 - 120 - ns address access time t aa - 100 - 120 ns chip select to output t co - 100 - 120 ns output enable to valid output t oe - 50 - 50 ns lb , ub valid to data output t ba - 100 - 120 ns chip select to low-z output t lz 10 - 10 - ns output enable to low-z output t olz 5 - 5 - ns lb , ub enable to low-z output t blz 10 - 10 - ns output hold from address change t oh 15 - 15 - ns chip disable to high-z output t hz 0 30 0 35 ns oe disable to high-z output t ohz 0 30 0 35 ns ub , lb disable to high-z output t bhz 0 30 0 35 ns write write cycle time t wc 100 - 120 - ns chip select to end of write t cw 80 - 100 - ns address set-up time t as 0 - 0 - ns address valid to end of write t aw 80 - 100 - ns write pulse width t wp 70 - 80 - ns write recovery time t wr 0 - 0 - ns write to output high-z t whz 0 30 0 35 ns data to write time overlap t dw 40 - 50 - ns data hold from write time t dh 0 - 0 - ns end write to output low-z t ow 5 - 5 - ns lb , ub valid to end of write t bw 80 - 100 - ns
km616s4110c family cmos sram preliminary revision 0.01 august 1998 6 address data out previous data valid data valid timming diagrams timing waveform of read cycle(1) (address controlled , cs 1 = oe =v il , cs 2 = we =v ih , ub or/and lb =v il ) timing waveform of read cycle(2) ( we =v ih ) data valid high-z t rc cs 1 address ub , lb oe data out t aa t rc t oh t oh t aa t co t ba t oe t olz t blz t lz t ohz t bhz t hz notes ( read cycle) 1. t hz and t ohz are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. at any given temperature and voltage condition, t hz (max.) is less than t lz (min.) both for a given device and from device to device interconnection. cs 2
km616s4110c family cmos sram preliminary revision 0.01 august 1998 7 timing waveform of write cycle(1) ( we controlled) address cs 1 data undefined ub , lb we data in data out timing waveform of write cycle(2) ( cs 1 controlled) address data valid ub , lb we data in data out high-z high-z t wc t cw(2) t wr(4) t aw t bw t wp(1) t as(3) t dh t dw t whz t ow t wc t cw(2) t aw t bw t wp(1) t dh t dw t wr(4) high-z high-z data valid t as(3) cs 2 cs 1 cs 2
km616s4110c family cmos sram preliminary revision 0.01 august 1998 8 address data valid ub , lb we data in data out high-z high-z timing waveform of write cycle(3) ( ub , lb controlled) notes (write cycle) 1. a wri t e occurs during the overlap(t wp ) of low cs 1 and low we . a write begins when cs 1 goes low and we goes low with asserting ub or lb for single byte operation or simultaneously asserting ub and lb for double byte operation. a write ends at the earliest tran- sition when cs 1 goes high and we goes high. the t wp is measured from the beginning of write to the end of write. 2. t cw is measured from the cs 1 going low to end of write. 3. t as is measured from the address valid to the beginning of write. 4. t wr is measured from the end or write to the address change. t wr applied in case a write ends as cs 1 or we going high. t wc t cw(2) t bw t wp(1) t dh t dw t wr(4) t aw data retention wave form cs 1 controlled v cc 2.3v 2.0v v dr cs , lb / ub gnd data retention mode cs 1 3 v cc - 0.2v t sdr t rdr t as(3) cs 1 cs 2 cs 2 controlled v cc 2.3v 0.4v v dr cs 2 gnd data retention mode t sdr t rdr cs 2 0.2v
km616s4110c family cmos sram preliminary revision 0.01 august 1998 9 package dimensions 6 5 4 3 2 1 a b c d e f g h c / 2 b/2 c b b1 c 1 ball #a1 b b/2 elastomer sram die c ball #a1 c / 2 bottom view top view d e 2 e 1 e c detail a side view 0 . 6 8 / t y p . 0 . 4 5 / t y p . 0 . 2 5 / t y p . a y elastomer 0.3/typ. die detail a notes. 1. bump counts : 48(8row x 6row) 2. bump pitch : (x,y)=(0.75 x 0.75)(typ.) 3. all tolerence are +/-0.050 unless otherwise specified. 4. typ : typical 5. y is coplanarity: 0.08(max) min typ max a - 0.75 - b 6.00 6.10 6.20 b1 - 3.75 - c 8.80 8.90 9.00 c1 - 5.25 - d 0.30 0.35 0.40 e - 0.93 0.94 e1 - 0.68 - e2 - 0.25 - y - - 0.08 units : millimeter
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